Various techniques have heretofore been used to package integrated circuits. For example, various configurations utilizing lead frames to connect integrated circuits have been developed, such as the flip chip design and the small outline J lead (SOJ) packaging techniques. In many of these prior techniques, the integrated circuit is mounted upon a pad provided by a lead frame, and wire bonds connect from the integrated circuit to conductive leads on the lead frame.
More recently, an integrated circuit packaging technique termed the lead on chip (LOC) technique has been developed. As described in the article entitled Volume Production Of Unique Plastic Surface-Mount Modules For The IBM 80-ns 1-Mbit DRAM Chip By Area Wire Bond Techniques by William C. Ward, published at the 38th ECC in 1988, this technique disposes a lead frame over the active area of an integrated circuit. Adhesive insulating tape connects the lead frame over the integrated circuit, and wire bonds connect the circuit directly to the power buses on the lead frame or jumper over the power buses to conductive leads to provide the correct signal routing. The ability to jump wires over various lead frame leads provides significant advantages by allowing alterable package I/O without chip redesign, since the wires can readily be routed over various buses or leads similar to conventional wire bonding as done on direct chip attached circuit cards.
While prior packaging techniques have worked well in practice for many designs, with the advent of more complex and smaller scale integrated circuits, it has become important to obtain equal loading capacitances for the input leads on the integrated circuit package. The provision of equal capacitances for various conductive leads is particularly significant for LOC applications, since the lead frame is separated from the active integrated circuit by a layer of dielectric. The requirement of equal capacitances for the conductive input leads has also become more important with the advent of large dynamic random access memory (DRAM) circuits such as the 16 meg DRAM. In such circuits, it is important that each address line has the same loading capacitance as the adjacent line in order to enhance the operational speed of the DRAM. Moreover, a need has arisen in the LOC package technique to provide additional noise shielding, which is particularly important in LOC devices because of the non-uniform metal closely adjacently disposed to the integrated circuit.
A need has thus arisen for a lead frame and integrated circuitry packaging technique which provides equal capacitances to all lead conductors associated with the integrated circuitry, while maintaining a high degree of noise shielding thereto.